1. Field of the Invention
The present invention relates in general to an electro-optical liquid crystal display suitable for finely graded operation and methods of driving and manufacturing the same.
2. Description of the Prior Art
Recently, thin film transistor liquid crystal displays (TFTLCD for short) have been increasingly broadly utilized, along with the development of color liquid crystal displays, rather than simple matrix type liquid crystal displays because the former type is particularly excellent in terms of brightness, contrast and wide view angles.
FIG. (A) is a circuit diagram showing a driving circuit for controlling one pixel of such a TFTLCD. As shown in the figure, a single thin film transistor is provided for the pixel located at each intersection of a matrix diagonal wiring comprising horizontal addressing lines (only one line VG being illustrated) and vertical data lines (also only one line VD being illustrated). The drain (D) of the transistor is connected to the corresponding one of the data lines while the source (S) thereof is connected to the corresponding one of the electrode pads defining pixels of the display (not shown). The gate of the transistor is connected to the corresponding one of the addressing lines VG. Such a matrix type design has been broadly employed already in the DRAM technique so that the reliability thereof is believed to have been fully established. In the case of the driving technique for liquid crystal display, however, there remain still several problems to be solved since the operation of liquid crystal displays includes also analog data manipulation.
FIG. 1(B) is a schematic diagram showing examples of signals applied to the addressing line VG and the data line VD and the resultant driving voltage at the electrode of the corresponding pixel in response to the signals. If a liquid crystal material is subjected to a DC voltage for a substantial time period, the characteristics of the materials are degraded. The signal at the data line therefore is periodically inverted (usually for each frame) in order to invert the direction of the voltage applied across the liquid crystal material.
The mechanism of the operation of the pixel is next explained. When a voltage pulse is applied to the gate, the transistor is turned on in order to transmit electric charge to the electrode pad of the pixel from the data line being at a high level so that the voltage level of the electrode pad is increased (region t1). The increase, however, is not so fast. In the case the transistor is made of an amorphous silicon semiconductor, the mobility of carriers is so low that the pulse applied to the gate is sometimes removed and the transistor is turned off before the voltage at the pixel reaches to the necessary level. In the case that the transistor is made of polysilicon, such undesirable situation is substantially improved. If the operational speed is so high that the pulse width is narrower than one microsecond, however, even the polysilicon transistor can no longer follow such a high speed. It takes 30 milliseconds in usual cases to scan one frame. The pulse width of the addressing signal is therefore about 50 microseconds in the case that the number of the addressing lines is 480 (480 rows display). If higher definition of grading is desired, however, the pulse width narrower than one microsecond becomes necessary.
The voltage at the pixel then drops by ΔV. This drop, called “rebound”, is caused by charge accumulated in the parasitic capacitance which is formed by the overlap between the gate electrode and the source region. The voltage drop increases as the parasitic capacitance increases. In the case of displays utilizing amorphous TFTs, a capacitance is provided across the liquid crystal at the pixel in order to reduce the voltage drop. The provision of such a particular capacitance, in turn, increases the load of the TFT and the other peripheral circuit and decreases the aperture ratio because of the wiring for the capacitances so that the brightness is decreased.
In the case of polysilicon transistors, such a problem of the voltage drop is not so significant since the self-alignment process can be employed for forming the gate electrode and the source and drain regions. The voltage drop, however, still exists as high as one volt which may become a substantial problem in the future when a higher definition is required.
The voltage at the pixel gradually decreases until a next addressing pulse arrives (region t2) because of discharge due mainly to leakage current passing through the transistor being turned off. The next pulse is then applied to the addressing line VG. Since the voltage level of the pulse is inverted in this time, the voltage level at the pixel is also gradually decreased to the inverted level in the same manner as described above.
When the addressing pulse is removed from the addressing line, the absolute value of the voltage at the pixel is increased in this case by the voltage drop ΔV followed by a gradual decrease due to discharge. As understood from the illustration, the voltage applied to the pixel is asymmetrical resulting in several problems such as flicker or deterioration of the liquid crystal material.
Furthermore, it is to be noted that the voltage at the pixel having a waveform of such a complicated pattern substantially tends to vary from pixel to pixel. For example, the rise of the voltage at the pixel in region t1 depends upon the several parameters of the transistor, e.g. the mobility, the channel length, the thickness of the active region, the gate voltage (the voltage applied to the addressing line) and the drain voltage (the voltage applied to the data line). The mobility of the transistor depends largely upon the manufacturing process so that pixel to pixel variation will not be so large. When the panel size becomes large in the future, however, it will be the case that the variation within the same panel can not be neglected. Variation in the thickness of the active region may be also a problem in the case of large panels. Variations in the channel length and the channel width are usually as large as about 10% or more from pixels near the driver to pixels apart from the driver.
The voltage drop depends upon the parasitic capacitance of the TFT. The dispersion of the capacitance is about 20% in the case of non-self alignment processes and about 10% in the case of self-alignment processes. Furthermore, since the voltage drop is in proportion to the gate voltage applied, the dispersion of the parasitic capacitance and the dispersion of the gate voltage form a multiplier action to widen the dispersion of the voltage drop.
On the other hand, the gradual decrease of the voltage at the pixel depends largely upon the channel length, the channel width, and the characteristics of the active region, and of the transistor (TFT). As a result, the voltage level at the pixel fluctuates from solid line to broken line in FIG. 1(B). Particularly accurate quality control is required in manufacturing processes for the devices in order that the dispersion of the voltage at the pixel is always within a tolerable range. As a result, the yield is significantly decreased. It may be impossible to meet future requirements for highly-value-added products with a high yield whereas low quality products may be manufactured with a relatively high yield.
At the present time, a plurality of grades in brightness can be constructed by controlling the voltages at the signal lines. The manufacture of the graded displays seems to be almost impossible even with 16 grades in accordance with the current technique from the view point as discussed below. The threshold voltages of usual twisted nematic liquid crystals are 5V or therearound, which are divided by 16 into 30 mV for realizing 16 grades. Considering dispersion in the voltage rise at time t1, in the voltage drop and in the discharge, as above discussed, the dispersion of the voltage at the pixel would easily exceed 300 mV unless products are carefully sifted out.
From the above view point, the inventors have advocated digital graded displaying systems in place of analog grading systems. The digital grading is realized by controlling the time for which the liquid crystal is subjected to a driving voltage at each pixel. Details are described in Japanese Patent Applications Nos. Hei3-169305, 169306, 169307 and 209869 of the same applicant. The frequencies required for driving the digital grading displays, however, are 20 to 300 times as high as conventional frequencies so that TFTs of CMOS structure have to be arranged at each pixel in place of NMOSTFT alone. It is also difficult even with such digital systems to suppress disturbance of grading due to dispersion of the characteristics of the TFTs.
For example, when an intermediate grade is selected by limiting the voltage application time only to 45% of one frame, 110% of the predetermined voltage level may be applied to certain pixels whereas 90% of the level may be applied to other pixels, in which case the display incurs 20% or wider dispersion of the driving voltage since 1.1×45%=49.5% in the former pixels and 0.9×45%=40.5% in the later pixels. In this case, only 8 grades seem to be possible.
In order to solve this problem, as described in Japanese Patent Application No. Hei3-209870, the inventors proposed for the driving device to collect information about characteristics of respective pixels and input the information into an external memory device. The input data signals are processed in advance on the basis of the information and outputted to the respective pixels in order to make correction. The data processing, however, is so complicated that peripheral circuits must carry heavy burdens. Furthermore, it takes a substantial time to examine the respective pixels and input correction data. For example, if the examination and the data input for one pixel take one second, the total time of 85 hours is necessary in the case of a panel having 640×480 pixels resulting in a significantly increased cost.